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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2000 mos integrated circuit pd442002-x 2m-bit cmos static ram 128k-word by 16-bit extended temperature operation data sheet document no. m14670ej6v0ds00 (6th edition) date published july 2001 ns cp (k) printed in japan the mark shows major revised points. description the pd442002-x is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) cmos static ram. the pd442002-x is packed in 48-pin tape fbga. features ? 131,072 words by 16 bits organization ? fast access time : 50, 55, 70, 85, 100, 120 ns (max.) ? byte data control : /lb (i/o1 - i/o8), /ub (i/o9 - i/o16) ? low voltage operation (bb version : v cc = 2.7 to 3.6 v, bc version : v cc = 2.2 to 3.6 v, dd version : v cc = 1.8 to 2.2 v) ? low v cc data retention : 1.0 v (min.) ? operating ambient temperature : t a = ?25 to +85 c ? output enable input for easy application part number access time operating supply operating ambient supply current ns (max.) voltage temperature at operating at standby at data retention v c ma (max.) a (max.) a (max.) pd442002-bbxxx 50 note 1 , 55, 70, 85 2.7 to 3.6 ? 25 to +85 30 note 2 42 35 note 3 40 note 4 pd442002-bcxxx 70, 85, 100 2.2 to 3.6 30 pd442002-ddxxx 85, 100, 120 1.8 to 2.2 15 3 notes 1. v cc 3.0 v 2. cycle time 70 ns 3. cycle time = 55 ns 4. cycle time = 50 ns
data sheet m14670ej6v0ds 2 pd442002-x ordering information part number package access time operating operating remark ns (max.) supply voltage temperature vc pd442002f9-bb55x-bc1 48-pin tape fbga (6 8) 55, 50 note 2.7 to 3.6 ? 25 to +85 bb version pd442002f9-bb70x-bc1 70 pd442002f9-bb85x-bc1 85 pd442002f9-bc70x-bc1 70 2.2 to 3.6 bc version pd442002f9-bc85x-bc1 85 pd442002f9-bc10x-bc1 100 pd442002f9-dd85x-bc1 85 1.8 to 2.2 dd version pd442002f9-dd10x-bc1 100 pd442002f9-dd12x-bc1 120 note v cc 3.0 v marking image part number marking (xx) pd442002f9-bb55x-bc1 b1 pd442002f9-bb70x-bc1 b2 pd442002f9-bb85x-bc1 b3 pd442002f9-bc70x-bc1 c2 pd442002f9-bc85x-bc1 c3 pd442002f9-bc10x-bc1 c4 pd442002f9-dd85x-bc1 d3 pd442002f9-dd10x-bc1 d4 pd442002f9-dd12x-bc1 d5 j s2m0-xx index mark lot no.
data sheet m14670ej6v0ds 3 pd442002-x pin configuration /xxx indicates active low signal. 48-pin tape fbga (6 8) [ pd442002f9-bbxxx-bc1 ] [ pd442002f9-bcxxx-bc1 ] [ pd442002f9-ddxxx-bc1 ] a b c d e f g h 1 2 3 4 5 6 bottom view 6 5 4 3 2 1 top view 123456 654321 a /lb /oe a0 a1 a2 nc a nc a2 a1 a0 /oe /lb b i/o9 /ub a3 a4 /cs i/o1 b i/o1 /cs a4 a3 /ub i/o9 c i/o10 i/o11 a5 a6 i/o2 i/o3 c i/o3 i/o2 a6 a5 i/o11 i/o10 d gnd i/o12 nc a7 i/o4 v cc dv cc i/o4 a7 nc i/o12 gnd ev cc i/o13 nc a16 i/o5 gnd e gnd i/o5 a16 nc i/o13 v cc f i/o15 i/o14 a14 a15 i/o6 i/o7 f i/o7 i/o6 a15 a14 i/o14 i/o15 g i/o16 nc a12 a13 /we i/o8 g i/o8 /we a13 a12 nc i/o16 h nc a8 a9 a10 a11 nc h nc a11 a10 a9 a8 nc a0 - a16 : address inputs i/o1 - i/o16 : data inputs / outputs /cs : chip select /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply gnd : ground nc : no connection remark refer to package drawing for the index mark.
data sheet m14670ej6v0ds 4 pd442002-x block diagram address buffer address buffer row decoder memory cell array 2,097,152 bits input data controller a0 a16 i/o9 - i/o16 column decoder /cs /we /oe /ub /lb output data controller i/o1 - i/o8 v cc gnd sense amplifier / switching circuit
data sheet m14670ej6v0ds 5 pd442002-x truth table /cs /oe /we /lb /ub mode i/o supply current i/o1 - i/o8 i/o9 - i/o16 h not selected high impedance high impedance i sb h h not selected high impedance high impedance lhhl output disable high impedance high impedance i cca l output disable high impedance high impedance l h l l word read d out d out l h lower byte read d out high impedance h l upper byte read high impedance d out lll word write d in d in l h lower byte write d in high impedance h l upper byte write high impedance d in remark : v ih or v il
data sheet m14670ej6v0ds 6 pd442002-x electrical specifications absolute maximum ratings parameter symbol product rating unit supply voltage v cc pd442002-bbxxx, pd442002-bcxxx ?0.5 note to +4.0 v pd442002-ddxxx ?0.5 note to +2.7 input / output voltage v t pd442002-bbxxx, pd442002-bcxxx ?0.5 note to v cc +0.4 (4.0 v max.) v pd442002-ddxxx ?0.5 note to v cc +0.4 (2.7 v max.) operating ambient temperature t a ?25 to +85 c storage temperature t stg ?55 to +125 c note ?3.0 v (min.) (pulse width : 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition pd442002-bbxxx pd442002-bcxxx pd442002-ddxxx unit min. max. min. max. min. max. supply voltage v cc 2.7 3.6 2.2 3.6 1.8 2.2 v high level input voltage v ih 2.7 v v cc 3.6 v 2.4 v cc +0.4 2.4 v cc +0.4 ? ? v 2.2 v v cc < 2.7 v ? ? 2.0 v cc +0.3 ? ? 1.8 v v cc < 2.2 v????1.6v cc +0.2 low level input voltage v il ?0.3 note +0.5 ?0.3 note +0.4 ?0.2 note +0.2 v operating ambient t a ?25 +85 ?25 +85 ?25 +85 c temperature note ?1.0 v (min.) (pulse width : 20 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are not 100% tested.
data sheet m14670ej6v0ds 7 pd442002-x dc characteristics (recommended operating conditions unless otherwise noted) (1/2) parameter symbol test condition pd442002-bbxxx unit min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /cs = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca1 /cs = v il , cycle time = 50 ns ? 40 ma i i/o = 0 ma, cycle time = 55 ns ? 35 minimum cycle time cycle time 70 ns ? 30 i cca2 /cs = v il , i i/o = 0 ma, cycle time = ?4 i cca3 /cs 0.2 v, cycle time = 1 s, i i/o = 0 ma, ? 4 v il 0.2 v, v ih v cc ? 0.2 v standby supply current i sb /cs = v ih or /lb = /ub = v ih ?0.6ma i sb1 /cs v cc ? 0.2 v 0.3 4 a i sb2 /lb = /ub v cc ? 0.2 v, /cs 0.2 v 0.3 4 high level output voltage v oh i oh = ?0.5 ma 2.4 v low level output voltage v ol i ol = 1.0 ma 0.4 v remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of product classification.
data sheet m14670ej6v0ds 8 pd442002-x dc characteristics (recommended operating conditions unless otherwise noted) (2/2) parameter symbol test condition pd442002-bcxxx pd442002-ddxxx unit min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /cs = v ih or ?1.0 +1.0 ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca1 /cs = v il , i i/o = 0 ma, ? 30 ? ? ma minimum cycle time v cc 2.7 v ? 25 ? ? v cc 2.2 v ? ? ? 15 i cca2 /cs = v il , i i/o = 0 ma, ? 4 ? ? cycle time = v cc 2.7 v ? 2 ? ? v cc 2.2 v ? ? ? 1 i cca3 /cs 0.2 v, cycle time = 1 s, ? 4 ? ? i i/o = 0 ma, v il 0.2 v, v cc 2.7 v ? 3 ? ? v ih v cc ? 0.2 v v cc 2.2 v ? ? ? 3 standby supply current i sb /cs = v ih or /lb = /ub = v ih ?0.6 ? ?ma v cc 2.7 v ? 0.6 ? ? v cc 2.2 v ? ? ? 0.6 i sb1 /cs v cc ? 0.2 v 0.3 4 ? ? a v cc 2.7 v 0.25 3.5 ? ? v cc 2.2 v ? ? 0.2 3 i sb2 /lb = /ub v cc ? 0.2 v, 0.3 4 ? ? /cs 0.2 v v cc 2.7 v 0.25 3.5 ? ? v cc 2.2 v ? ? 0.2 3 high level output voltage v oh i oh = ?0.5 ma 2.4 ? v v cc 2.7 v 1.8 ? v cc 2.2 v ? 1.5 low level output voltage v ol i ol = 1.0 ma 0.4 ? v v cc 2.7 v 0.4 ? v cc 2.2 v ? 0.4 remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of product classification.
data sheet m14670ej6v0ds 9 pd442002-x ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions [ pd442002-bb55x, pd442002-bb70x, pd442002-bb85x ] input waveform (rise and fall time 5 ns) 0.1 v cc 0.9 v cc test points v cc /2 v cc /2 output waveform test points v cc /2 v cc /2 output load 1ttl + 50 pf [ pd442002-bc70x, pd442002-bc85x, pd442002-bc10x ] input waveform (rise and fall time 5 ns) 0.1 v cc 0.9 v cc test points v cc /2 v cc /2 output waveform test points v cc /2 v cc /2 output load 1ttl + 30 pf [ pd442002-dd85x, pd442002-dd10x, pd442002-dd12x ] input waveform (rise and fall time 5 ns) 0.1 v cc 0.9 v cc test points v cc /2 v cc /2 output waveform test points v cc /2 v cc /2 output load 1ttl + 30 pf
data sheet m14670ej6v0ds 10 pd442002-x read cycle (1/3) (bb version) parameter symbol pd442002-bb55x pd442002 pd442002 unit condition v cc 3.0 v -bb70x -bb85x min. max. min. max. min. max. min. max. read cycle time t rc 50 55 70 85 ns address access time t aa 50 55 70 85 ns note 1 /cs access time t acs 50 55 70 85 ns /oe to output valid t oe 30 30 35 40 ns /lb, /ub to output valid t ba 50 55 70 85 ns output hold from address change t oh 10 10 10 10 ns /cs to output in low impedance t lz 10 10 10 10 ns note 2 /oe to output in low impedance t olz 5555ns /lb, /ub to output in low impedance t blz 10 10 10 10 ns /cs to output in high impedance t hz 20 20 25 30 ns /oe to output in high impedance t ohz 20 20 25 30 ns /lb, /ub to output in high impedance t bhz 20 20 25 30 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. read cycle (2/3) (bc version) parameter symbol pd442002 pd442002 pd442002 unit condition -bc70x -bc85x -bc10x min. max. min. max. min. max. read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns note 1 /cs access time t acs 70 85 100 ns /oe to output valid t oe 35 40 50 ns /lb, /ub to output valid t ba 70 85 100 ns output hold from address change t oh 10 10 10 ns /cs to output in low impedance t lz 10 10 10 ns note 2 /oe to output in low impedance t olz 555ns /lb, /ub to output in low impedance t blz 10 10 10 ns /cs to output in high impedance t hz 25 30 35 ns /oe to output in high impedance t ohz 25 30 35 ns /lb, /ub to output in high impedance t bhz 25 30 35 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf.
data sheet m14670ej6v0ds 11 pd442002-x read cycle (3/3) (dd version) parameter symbol pd442002 pd442002 pd442002 unit condition -dd85x -dd10x -dd12x min. max. min. max. min. max. read cycle time t rc 85 100 120 ns address access time t aa 85 100 120 ns note 1 /cs access time t acs 85 100 120 ns /oe to output valid t oe 40 50 60 ns /lb, /ub to output valid t ba 85 100 120 ns output hold from address change t oh 10 10 10 ns /cs to output in low impedance t lz 10 10 10 ns note 2 /oe to output in low impedance t olz 555ns /lb, /ub to output in low impedance t blz 10 10 10 ns /cs to output in high impedance t hz 30 35 40 ns /oe to output in high impedance t ohz 30 35 40 ns /lb, /ub to output in high impedance t bhz 30 35 40 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf.
data sheet m14670ej6v0ds 12 pd442002-x read cycle timing chart t rc t oh t hz t blz t ba t lz t acs t bhz t aa high impedance data out /lb, /ub (input) /cs (input) address (input) i/o (output) t olz t oe t ohz /oe (input) remark in read cycle, /we should be fixed to high level.
data sheet m14670ej6v0ds 13 pd442002-x write cycle (1/3) (bb version) parameter symbol pd442002-bb55x pd442002 pd442002 unit condition v cc 3.0 v -bb70x -bb85x min. max. min. max. min. max. min. max. write cycle time t wc 50 55 70 85 ns /cs to end of write t cw 45 50 55 70 ns /lb, /ub to end of write t bw 45 50 55 70 ns address valid to end of write t aw 45 50 55 70 ns address setup time t as 0000ns write pulse width t wp 40 45 50 55 ns write recovery time t wr 0000ns data valid to end of write t dw 25 25 30 35 ns data hold time t dh 0000ns /we to output in high impedance t whz 20 20 25 30 ns note output active from end of write t ow 5555ns note the output load is 1ttl + 5 pf. write cycle (2/3) (bc version) parameter symbol pd442002 pd442002 pd442002 unit condition -bc70x -bc85x -bc10x min. max. min. max. min. max. write cycle time t wc 70 85 100 ns /cs to end of write t cw 55 70 80 ns /lb, /ub to end of write t bw 55 70 80 ns address valid to end of write t aw 55 70 80 ns address setup time t as 000ns write pulse width t wp 50 55 60 ns write recovery time t wr 000ns data valid to end of write t dw 30 35 40 ns data hold time t dh 000ns /we to output in high impedance t whz 25 30 35 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf.
data sheet m14670ej6v0ds 14 pd442002-x write cycle (3/3) (dd version) parameter symbol pd442002 pd442002 pd442002 unit condition -dd85x -dd10x -dd12x min. max. min. max. min. max. write cycle time t wc 85 100 120 ns /cs to end of write t cw 70 80 100 ns /lb, /ub to end of write t bw 70 80 100 ns address valid to end of write t aw 70 80 100 ns address setup time t as 000ns write pulse width t wp 55 60 85 ns write recovery time t wr 000ns data valid to end of write t dw 35 40 60 ns data hold time t dh 000ns /we to output in high impedance t whz 30 35 40 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf.
data sheet m14670ej6v0ds 15 pd442002-x write cycle timing chart 1 (/we controlled) t wc t cw t bw t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address (input) /cs (input) /lb, /ub (input) i/o (input / output) t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during the overlap time of a low level /cs, a low level /we and a low level /lb (or low level /ub). 2. if /cs changes to low level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance.
data sheet m14670ej6v0ds 16 pd442002-x write cycle timing chart 2 (/cs controlled) t wc t as t cw t dw t dh data in high impedance address (input) /cs (input) /lb, /ub (input) i/o (input) high impedance t aw t wp t wr /we (input) t bw cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /cs, a low level /we and a low level /lb (or low level /ub).
data sheet m14670ej6v0ds 17 pd442002-x write cycle timing chart 3 (/lb, /ub controlled) t wc t dw t dh data in high impedance address (input) /lb, /ub (input) i/o (input) high impedance t aw t wp t wr /we (input) t as t bw /cs (input) t cw cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /cs, a low level /we and a low level /lb (or low level /ub).
data sheet m14670ej6v0ds 18 pd442002-x low v cc data retention characteristics (t a = ?25 to +85 c) parameter symbol test condition pd442002 pd442002 pd442002 unit -bbxxx -bcxxx -ddxxx min. typ. max. min. typ. max. min. typ. max. data retention v ccdr1 /cs v cc ? 0.2 v 1.0 3.6 1.0 3.6 1.0 2.2 v supply voltage v ccdr2 /lb = /ub v cc ? 0.2 v, 1.0 3.6 1.0 3.6 1.0 2.2 /cs 0.2 v data retention i ccdr1 v cc = 1.2 v, /cs v cc ? 0.2 v 0.15 2 0.15 2 0.15 2 a supply current i ccdr2 v cc = 1.2 v, /lb = /ub v cc ? 0.2 v, 0.15 2 0.15 2 0.15 2 /cs 0.2 v chip deselection t cdr 000ns to data retention mode operation t r t rc note t rc note t rc note ns recovery time note t rc : read cycle time
data sheet m14670ej6v0ds 19 pd442002-x data retention timing chart (1) /cs controlled v ih (min.) v ccdr (min.) v il (max.) /cs /cs v cc ? 0.2 v gnd v cc (min.) note t cdr data retention mode t r v cc note bb version : 2.7 v, bc version : 2.2 v, dd version : 1.8 v remark on the data retention mode by controlling /cs, the other pins (address, i/o, /we, /oe, /lb, /ub) can be in high impedance state. (2) /lb, /ub controlled t cdr data retention mode v ih (min.) v ccdr (min.) v il (max.) t r /lb, /ub /lb, /ub v cc ? 0.2 v gnd v cc v cc (min.) note note bb version : 2.7 v, bc version : 2.2 v, dd version : 1.8 v remark on the data retention mode by controlling /lb and /ub, the input level of /cs must be v cc ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state.
data sheet m14670ej6v0ds 20 pd442002-x package drawing 48-pin tape fbga (6x8) item millimeters d 8.0 0.1 6.0 0.1 a b x e 0.96 0.10 a1 0.25 0.05 w e 0.2 0.75 p48f9-75-bc1-1 a2 0.71 y 0.1 y1 0.1 0.35 0.05 0.08 zd 1.375 ze 1.125 a a1 zd a2 index mark ze s wb s wa s b b e a s y s y1 ? s x ab m d e
data sheet m14670ej6v0ds 21 pd442002-x recommended soldering conditions please consult with our sales offices for soldering conditions of the pd442002-x. types of surface mount device pd442002f9-bbxxx-bc1 : 48-pin tape fbga (6x8) pd442002f9-bcxxx-bc1 : 48-pin tape fbga (6x8) pd442002f9-ddxxx-bc1 : 48-pin tape fbga (6x8)
data sheet m14670ej6v0ds 22 pd442002-x [ memo ]
data sheet m14670ej6v0ds 23 pd442002-x notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd442002-x m8e 00. 4 the information in this document is current as of july, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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